本帖最后由 lintel 于 2010-3-1 20:10 编辑
根据来自RDC官方的Data Sheet,RDC R3210（也就是AMRISC 20000）是可以支持128M的内存的。但是，Data Sheet里面的说明，RDC R8610只有CSn0 CSn1，只有两个片选。如何实现两片内存达到128M呢？答案很简单，就是两片SD 512Mbitx16Bit x4Bank。
通过上图就可以看到.第62针就是CSn1。但是MGB100上，并没有接出来，对于双片内存，我们需要从62脚接出CSn1，让CPU用来选择内存芯片。
下面是RDC的Data Sheet：
参考关于Data Sheet第130页中的内存寄存器设置如下:
Register Offset: 66h
Register Name: Memory Clock Phase Selection Register
Reset Value: 00h
7 6 5 4 3 2 1 0
MCPS_R MCPS_W
Bit Name Attribute Description
7-4 MCPS_R R/W Memory Clock Phase Selection for Read.
3-0 MCPS_w R/W Memory Clock Phase Selection for Write.
Register Offset: 69h – 68h
Register Name: Memory Timing Register
Reset Value: C99Fh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tWR tRC tRP tRCD Reserved
Bit Name Attribute Description
15 tWR R/W
SDRAM cycle: Write Recovery Time.
0: 1T
1: 2T
14-11 tRC R/W
SDRAM cycle: REF/ACT to REF/ACT delay
Bit 14 Bit 13 Bit 12 Bit 11 delay period
0 0 0 0 Reserved
0 0 0 1 1 Clock
0 0 1 0 2 Clocks
0 0 1 1 3 Clocks
0 1 0 0 4 Clocks
0 1 0 1 5 Clocks
0 1 1 0 6 Clocks
0 1 1 1 7 Clocks
1 0 0 0 8 Clocks
1 0 0 1 9 Clocks
1 0 1 0 10 Clocks
1 0 1 1 11 Clocks
1 1 0 0 12 Clocks
1 1 0 1 13 Clocks
1 1 1 0 14 Clocks
1 1 1 1 15 Clocks
10-7 tRP R/W
SDRAM cycle: PRE to ACT command period
Bit 10 Bit 9 Bit 8 Bit 7 delay period
0 0 0 0 Reserved
0 0 0 1 1 Clock
0 0 1 0 2 Clocks
0 0 1 1 3 Clocks
0 1 0 0 4 Clocks
0 1 0 1 5 Clocks
0 1 1 0 6 Clocks
0 1 1 1 7 Clocks
1 0 0 0 8 Clocks
1 0 0 1 9 Clocks
1 0 1 0 10 Clocks
1 0 1 1 11 Clocks
1 1 0 0 12 Clocks
1 1 0 1 13 Clocks
1 1 1 0 14 Clocks
1 1 1 1 15 Clocks
6-3 tRCD R/W
SDRAM cycle: ACT to R/W command delay period
Bit 6 Bit 5 Bit 4 Bit 3 delay period
0 0 0 0 Reserved
0 0 0 1 1 Clock
0 0 1 0 2 Clocks
0 0 1 1 3 Clocks
0 1 0 0 4 Clocks
0 1 0 1 5 Clocks
0 1 1 0 6 Clocks
0 1 1 1 7 Clocks
1 0 0 0 8 Clocks
1 0 0 1 9 Clocks
1 0 1 0 10 Clocks
1 0 1 1 11 Clocks
1 1 0 0 12 Clocks
1 1 0 1 13 Clocks
1 1 1 0 14 Clocks
1 1 1 1 15 Clocks
2-0 Rsvd RO Reserved.
Register Offset: 6Bh – 6Ah
Register Name: Memory Control Register
Reset Value: 0004h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved LMR CasLat Rsvd
Bit Name Attribute Description
15-4 Rsvd RO Reserved
3 LMR R/W
Lode Mode Register. When this register is written by software, this bit is set by the DRAM
controller to program the mode register of SDRAM. After the programming is complete, this bit
will be auto-cleared by the DRAM controller.
0: Complete.
1: Programming the mode register of SDRAM.
2-1 CasLat R/W
SDRAM cycle: Cas Latency
Bit 2 Bit 1 delay period
0 0 Reserved
0 1 Reserved
1 0 2 Clocks
1 1 3 Clocks
0 Rsvd RO Reserved.
Register Offset: 6Dh – 6Ch
Register Name: Memory Bank Register
Reset Value: 0331h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved C1M BWT SS RAT BN CAT
Bit Name Attribute Description
15-14 Rsvd RO Reserved
13 C1M RW SDRAM CS_n[1] Mask when set. CS_n[1] is activated when cleared.
12 BWT RW
SDRAM Data Bus Width Type.
0: 16-bit.
1: Reserved.
11-8 SS RW
SDRAM Size:
Bit 11 Bit 10 Bit 9 Bit 8 SDRAM Size
0 0 0 0 2MB
0 0 0 1 4MB
0 0 1 0 8MB
0 0 1 1 16MB
0 1 0 0 32MB
0 1 0 1 64MB
0 1 1 0 128MB
0 1 1 1 Reserved
1 x x x Reserved
7-5 RAT RW
SDRAM Row Address Type:
Bit 7 Bit 6 Bit 5 No. Bits of Row Address
参考了RDC的CPU INIT.在里面关于内存的初始化说明如下：
1. SDRAM PHASE ;;
Setting SDRAM PHASE
mov
dx,0CF8h
mov
eax, 080000068h
out
dx, eax
mov
dx, 0CFCh
mov
eax, 00006C99Fh
out
dx, eax
2. SDRAM Delay Line and Bank control
It depends on what kind of SDRAM you used SDRAM 64M case (NANYA NT5SV16M16BS-75B * 2) ;;
Setting DelayLine value
mov
dx,0CF8h
mov
eax, 080000064h
out
dx, eax
mov
dx, 0CFCh
in
eax, dx
and
eax, 0FF00FFFFh
or
eax, 0009b0000h
out
dx, eax
;;
Setting Memory bank register
mov
dx,0CF8h
mov
eax, 08000006Ch
out
dx, eax
mov
dx, 0CFCh
mov
eax, 000000551h
out
dx, eax
SDRAM 32M case (NANYA NT5SV16M16BS-75B * 1) ;;
Setting DelayLine value
mov
dx,0CF8h
mov
eax, 080000064h
out
dx, eax
mov
dx, 0CFCh
in
eax, dx
and
eax, 0FF00FFFFh
or
eax, 000790000h
out
dx, eax
;;Setting Memory bank register
mov
dx,0CF8h
mov
eax, 08000006Ch
out
dx, eax
mov
dx, 0CFCh
mov
eax, 000000451h
out
dx, eax
3. Enable Timer2 for SDRAM refresh
;;Init DRAM refresh
mov
dx, 0043h
mov
al, 054h
out
dx, ax
mov
dx, 0041h
mov
al, 012h
out
dx, al
同样的，参考了RDC对Redboot的patch.
Romboot.s修改如下：
#==============================================================================
// .file "romboot.S"
#------------------------------------------------------------------------------
.code16
romboot_start:
/* Disable interrupt handling. */
cli
# Set DS == CS
movw %cs,%ax
movw %ax,%ds
# set ES == 0
movw $0,%ax
movw %ax,%es
# hlin ->
# init chipset
movw $0x4d0,%dx # master interrupt
movb $0x20,%al # irq5 level, others edge
outb %al,%dx
incw %dx # slave interrupt
movb $0xde,%al # irq15,14,12,11,10,9 level; others edge
outb %al,%dx
# init DRAM refresh
movw $0x43,%dx #
movb $0x54,%al #
outb %al,%dx
movw $0x41,%dx #
movb $0x12,%al #
outb %al,%dx
# enable L1 cache
# invd
# movl %cr0,%eax
# andl $0x9fffffff, %eax
# movl %eax,%cr0
# init north bridge
movw $0xcf8,%dx
movl $0x8000006c,%eax # memory
outl %eax,%dx
movb $0xfc,%dl
# movl $0x00000532,%eax # memory size = 64 FPGA
movl $0x00000451,%eax # memory size = 32 EVB
#movl $0x00000551,%eax # memory size = 64 EVB
# movl $0x00000331,%eax # memory size = 16 Demo (-6 for 166mhz)
outl %eax,%dx
movw $0xcf8,%dx
movl $0x80000070,%eax #
outl %eax,%dx
movb $0xfc,%dl
movl $0x04000003,%eax #
outl %eax,%dx
# delay line for Memory
movw $0xcf8,%dx
movl $0x80000064,%eax #
outl %eax,%dx
movb $0xfc,%dl
inl %dx,%eax
andl $0xff00ffff,%eax
orl $0x009b0000,%eax # 79 for 32M, 9B for 64M
# orl $0x00790000,%eax # 79 for 32M, 9B for 64M
outl %eax,%dx
对比发现，单片32M与双片32M的设置
废话就不多说了，下面是我的理论，希望有条件的兄弟试试。
1.64M内存方案
方案1：单片SD 512Mbit(64MByte)x16Bit x4Bank。
方案2:
两片SD 256Mbit(32MByte)x16Bit x4Bank。
首先，需要两片内存叠焊
实现64M内存的方式比较简单。
2.128M内存方案
未完成。。。编辑中。 |
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发表于 2010-2-22 19:08
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